This invention relates to the structure and operation of semiconductor memories; and more particularly, it relates to static BiCMOS memories having dual read ports.
In a static memory, data is stored in each memory cell on a pair of transistors which are cross-coupled to each other. These cross-coupled transistors form a set node and a reset node of the cell. To store a digital 0 in the cell, one of the transistors is turned on while the other transistor is turned off; and to store a digital 1 in the cell, the on and off states of the transistors are reversed All of this is in comparison to a dynamic memory in which each cell consists of a single transistor and a capacitor; and data is stored in the cell by charging or discharging the capacitor.
In the prior art, static memory cells with dual read ports have been disclosed which are made of all field-effect transistors. See, for example, the article entitled "The Twin Port Memory Cell" by K. O'Connor, IEEE Journal of Solid State Circuits, Vol. SC-22 No. 5, October 1987. In that article, FIG. 2 shows two structures for an NMOS memory cell having dual read ports, and FIG. 4 shows one structure for a CMOS memory cell having dual read ports. However, a drawback of a memory cell that is made of all field-effect transistors is that the reading of data from the cell is inherently slow. This, in part, is due to the fact that during a read operation, the bit lines to which the cell connects must be charged or discharged; and field-effect transistors provide no current gain for speeding up this charging operation.
By comparison, with a BiCMOS static memory cell, this problem is overcome. Such a cell is described in the prior art in a paper entitled "On the Analysis and Design of a CMOS-Bipolar SRAMs" by De Los Santos et al in the IEEE Journal of Solid State Circuits, Vol. SC-22 No. 4,August 1987. There, the set and reset nodes of the memory cells are coupled to the bit lines through respective bipolar transistors, and each bipolar transistor provides a current gain. Typically, this current gain is in the range of fifty to one hundred; and, the bit lines charge with a speed that is proportional to the magnitude of that current gain.
However, BiCMOS memory cells of the prior art are deficient in that they do not have dual read ports. Also, in attempting to add a second read port to a single port BiCMOS cell, care must be taken to not add too many extra components; otherwise the cell will be too big for use in large memory cell arrays Further, since computer systems which read memory cells tend to get faster and faster, any modification to a memory which increases the cell's read speed beyond conventional BiCMOS would be a major improvement.
Accordingly, a primary object of the invention is to provide an improved BiCMOS memory cell in which the above problems are overcome.